This application is based on application Nos. 11-30478, 11-30479, 11-30480, 11-38794 and 11-47078 filed in Japan, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor chips for a so-called chip-on-chip structure which includes a plurality of semiconductor chips bonded in a double-stacked relation, chip-on-chip semiconductor devices, and chip-on-chip mounting methods.
2. Description of Related Art
For size reduction and higher integration of semiconductor devices, a proposal has been made to shift the design concept from a conventional two-dimensional structure to a three-dimensional structure.
However, production of semiconductor devices of three-dimensional structure through a continuous process often encounters difficulties such as a lower yield.
The inventors of the present invention have been conducting studies on practical applications of a semiconductor device of a so-called chip-on-chip structure which includes a plurality of semiconductor chips bonded to one another in a face-to-face double-stacked relation.
Where semiconductor chips are bonded to each other in a stacked relation, for example, where a relatively small secondary chip is laid on the front face of a relatively large primary chip, the secondary chip can easily be positioned in alignment with the primary chip with the front face thereof upward and with the back face thereof opposed to the front face of the primary chip.
However, if an attempt is made to stack the primary chip and the secondary chip in a face-to-face relation, there is a difficulty in aligning these semiconductor chips with each other. This is because the orientation of a semiconductor chip, the arrangement of electrodes on the front face of the semiconductor chip and the like cannot be checked from the back side thereof.
Particularly, the electrodes are not always arranged in a predetermined positional relationship with the profile of the semiconductor chip, but the positional relationship between the electrode arrangement and the profile varies depending on dicing conditions under which a semiconductor wafer is diced into semiconductor chips. Therefore, it is difficult to align or position the semiconductor chips with respect to each other by viewing either of the semiconductor chips from the back side thereof.
Even if the primary and secondary chips have substantially the same size, the alignment of the semiconductor chips for bonding thereof is difficult.
In view of the foregoing, it is a principal object of the present invention to provide a chip-on-chip structure which includes a plurality of semiconductor chips bonded to one another in a face-to-face stacked relation for practical applications.
It is another object of the invention to provide a semiconductor chip for chip-on-chip mounting to provide the chip-on-chip structure for practical applications.
It is further another object of the invention to provide a chip-on-chip semiconductor device and a mounting method therefore.
A feature of the present invention is generally to provide marks such as an electrode mark, a back mark and an alignment mark on the back face of a semiconductor chip for recognition of the orientation of the semiconductor chip and the electrode arrangement on the semiconductor chip.
More specifically, (in accordance with an inventive aspect, there is provided a semiconductor chip for a chip-on-chip structure in which a plurality of semiconductor chips are bonded to one another in a stacked relation with electrode-carrying front faces thereof opposed to each other, the semiconductor chip comprising an electrode mark provided on a back face thereof in association with an electrode provided on a front face thereof.
In accordance with an inventive aspect, the semiconductor chip for the chip-on-chip structure according to claim 1 is characterized in that a plurality of electrodes are provided in a predetermined arrangement on the front face of the semiconductor chip, and a plurality of electrode marks are provided on the back face of the semiconductor chip in association with respective electrodes and in the same arrangement as the electrode arrangement.
In accordance with an inventive aspect, a semiconductor chip for a chip-on-chip structure is characterized in that a plurality of electrodes are provided in a predetermined arrangement on the front face of the semiconductor chip, and electrode marks are provided on the back face of the semiconductor chip in association with predetermined ones of the plurality of electrodes.
In accordance with an inventive aspect, there is provided a chip-on-chip semiconductor device which comprises a plurality of semiconductor chips bonded to one another in a stacked relation with electrode-carrying front faces thereof opposed to each other via electrodes provided on the opposed front faces, wherein electrode marks are provided on a back face of at least one of the stacked semiconductor chips in association with the electrodes on the front face of the one semiconductor chip.
In accordance with an inventive aspect, there is provided a chip-on-chip mounting method for stacking first and second semiconductor chips each having electrodes provided on a front face thereof so that the electrodes on the first semiconductor chip are bonded to the electrodes on the second semiconductor chip, the method comprising the steps of: placing the first semiconductor chip with the front face thereof upward; and positioning the second semiconductor chip with respect to the first semiconductor chip on the basis of electrode marks provided on a back face of the second semiconductor chip in association with the electrodes provided on the front face of the second semiconductor chip to mount the second semiconductor chip on the first semiconductor chip with the front face of the second semiconductor chip facing downward as opposed to the front face of the first semiconductor chip.
With the arrangements above, when the chip-on-chip structure is assembled with the front face of the semiconductor chip downward, the positioning of the semiconductor chip can be achieved on the basis of the electrode marks provided on the back face of the semiconductor chip. The electrode marks on the back face of the semiconductor chip are located in association with the electrodes on the front face of the semiconductor chip. The electrode marks provided in association with the electrodes may each be defined, for example, as a mark which surrounds an intersection between the back face and a phantom vertical line extending vertically through the semiconductor chip from an electrode. In other words, the electrode marks are each defined as a mark of an electrode as seen through the semiconductor chip from the back side thereof.
Therefore, with the electrode marks, the positions of the electrodes can be checked from the back side of the semiconductor chip, so that the semiconductor chip can properly be positioned with its face down in a desired position on another semiconductor chip to be bonded thereto. As a result, the chip-on-chip structure can be produced with almost no offset between the opposed electrodes. Since the positioning of the semiconductor chips is easy, the time required for assembling the chip-on-chip structure can be reduced.
Although the electrode marks are provided in association with respective electrodes, the electrode marks may be provided in association with specific ones of the electrodes for the purpose of the proper positioning of the semiconductor chip. For example, four electrode marks may be provided in association with electrodes disposed in four corners of the semiconductor chip.
With the arrangement according to one aspect of the instant invention, the chip-on-chip semiconductor device is provided in which the opposed electrodes are bonded to each other with a high level of precision, and the electrode positions of the semiconductor device can be checked. Further, it can be easily checked if the chip-on-chip semiconductor device is produced by employing one of the semiconductor chips above.
With the arrangement according to one aspect of the invention, the chip-on-chip structure can be assembled by utilizing the electrode marks. In other words, the chip-on-chip mounting method provides an assembling method for a chip-on-chip semiconductor device, which can be employed for practical applications on actual production lines.
In accordance with an inventive aspect, there is provided a primary semiconductor chip serving as a base to be mounted with a secondary semiconductor chip with a front face thereof bonded to a secondary semiconductor chip, the primary semiconductor chip comprising a mark provided on the front face thereof to be utilized as a positioning reference mark when the primary and secondary semiconductor chips are to be stacked.
In accordance with an inventive aspect, the primary semiconductor chip is characterized in that a plurality of secondary semiconductor chips are to be mounted on the front face of the primary semiconductor chip, and different positioning reference marks are provided on the front face of the primary semiconductor chip in association with chip mounting positions in which the respective secondary semiconductor chips are to be mounted.
In accordance with an inventive aspect, there is provided a method for mounting a secondary semiconductor chip on a front face of a primary semiconductor chip serving as a base, the method comprising the steps of: providing on the front face of the primary semiconductor chip a mark which serves as a positioning reference mark when the primary and secondary semiconductor chips are to be stacked; and positioning the secondary semiconductor chip on the front face of the primary semiconductor chip on the basis of the positioning reference mark.
With the arrangements above, the secondary semiconductor chip can be positioned with respect to the primary semiconductor chip on the basis of the positioning reference mark provided on the front face of the primary semiconductor chip.
Where the secondary semiconductor chip is to be mounted on the primary semiconductor chip, for example, with the use of mechanical hands by determining positioning coordinates for the secondary semiconductor chip on the basis of a profile-based positional relationship between the primary semiconductor chip and the secondary semiconductor chip, the positioning control is difficult.
This is because electrodes arranged on front faces of the semiconductor chips generally have a size on the order of 100i and an allowable offset for the positioning of the semiconductor chips with the opposed electrodes of a size of 100i aligned with each other is supposedly about xc2x15 to 10i. 
However, the positioning offset cannot be accommodated within the aforesaid allowable range where the positioning is based on the positioning coordinates for the secondary semiconductor chip determined on the basis of the positional relationship between the primary semiconductor chip and the secondary semiconductor chip.
This is why the positioning of the secondary semiconductor chip is based on the positioning reference mark preliminarily provided on the front face of the primary semiconductor chip in accordance with the present invention.
Thus, the secondary semiconductor chip can properly be positioned with respect to the primary semiconductor chip with a positioning offset within the aforesaid allowable range.
The positioning reference mark is not necessarily required to have a great size but is preferably formed as a pin-point mark. This is because an image processing can more easily be performed on the pin-point mark for easy positioning of the secondary semiconductor chip.
The front face of the primary semiconductor chip is generally covered with a passivation film, so that the mark can be provided in any desired position.
With one of the arrangements above, the different positioning reference marks for the respective secondary semiconductor chips to be mounted on the primary semiconductor chip are provided on the front face of the primary semiconductor chip. This ensures easy image processing for properly positioning the plurality of secondary semiconductor chips in the predetermined positions on the primary semiconductor chip.
In accordance with an inventive aspect, there is provided a semiconductor chip for a chip-on-chip structure in which a plurality of semiconductor chips are bonded to one another in a face-to-face stacked relation, the semiconductor chip comprising a back mark provided on a back face thereof for recognition of orientation thereof and electrode arrangement thereon.
The back mark preferably includes at least two back marks.
The back mark preferably includes a tally mark which is to be brought into a predetermined positional relationship with a front mark provided on a front face of another semiconductor chip to be bonded to the semiconductor chip in a stacked relation.
With the provision of the back mark on the back face of the semiconductor chip for the chip-on-chip structure, the semiconductor chip can be positioned with respect to the another semiconductor chip on the basis of the back mark for formation of the chip-on-chip structure.
Particularly with the provision of two or more back marks, the orientations of the semiconductor chips to be stacked can correctly be checked on the basis of the two or more back marks.
Where the back mark is provided on one of the semiconductor chips and the front mark is provided on the other semiconductor chip, the semiconductor chips to be stacked can more easily be positioned with respect to each other by bringing the back mark and the front mark into a predetermined positional relationship. This arrangement is particularly effective where the two semiconductor chips to be stacked have different sizes. Further, this arrangement is advantageous in that proper positioning of the stacked semiconductor chips can be checked on the basis of the positional relationship between the front mark and the back mark after the assembling of the chip-on-chip structure.
Thus, the back mark provided on the semiconductor chip allows the semiconductor chip to be assembled into the chip-on-chip structure on a production line and the like. Since the positioning of the semiconductor chips with respect to each other can easily be achieved, the time required for assembling the chip-on-chip structure is effectively reduced.
In accordance with an inventive aspect the semiconductor chip for the chip-on-chip structure is characterized in that one of the plurality of semiconductor chips is a primary chip to be disposed with the front face thereof upward, and another of the plurality of semiconductor chips is a secondary chip to be bonded onto the primary chip with the front face thereof facing downward as opposed to the front face of the primary chip, and in that the back mark is provided on the secondary chip.
With this arrangement, the secondary chip can easily be positioned with respect to the primary chip when the primary and secondary chips are to be bonded to each other in a stacked relation. Particularly, when the secondary chip is to be mounted on the primary chip preliminarily positioned, the positioning of the secondary chip can easily be achieved.
In accordance with an inventive aspect the semiconductor chip for the chip-on-chip structure is characterized in that one of the plurality of semiconductor chips is a primary chip to be disposed with the front face thereof upward, and another of the plurality of semiconductor chips is a secondary chip to be bonded onto the primary chip with the front face thereof facing downward as opposed to the front face of the primary chip, and in that the back mark is provided on the primary chip.
With this arrangement, the primary chip can easily be positioned with respect to the secondary chip preliminarily positioned, or the positioning of the secondary chip can be controlled on the basis of the back mark on the primary chip.
In accordance with an inventive aspect, the semiconductor chip for the chip-on-chip structure is characterized in that one of the plurality of semiconductor chips is a primary chip to be disposed with the front face thereof upward, and another of the plurality of semiconductor chips is a secondary chip to be bonded onto the primary chip with the front face thereof facing downward as opposed to the front face of the primary chip, and in that the primary chip and the secondary chip are each provided with the back mark.
This arrangement is advantageous not only where either the primary chip or the secondary chip is preliminarily positioned but also where the primary and secondary chips each held by a robot arm or the like are positioned with respect to each other.
In accordance with an inventive aspect, the semiconductor chip for the chip-on-chip structure is characterized in that one of the plurality of semiconductor chips is a primary chip to be disposed with the front face thereof upward, and another of the plurality of semiconductor chips is a secondary chip to be bonded onto the primary chip with the front face thereof facing downward as opposed to the front face of the primary chip, and in that the front mark is provided on the front face of the primary chip and the back mark is provided on the secondary chip in a predetermined positional relationship with the front mark on the primary chip.
This arrangement is advantageous in that the primary and secondary chips can easily be positioned with respect to each other and whether or not any offset occurs between the primary and secondary chips can be checked after the chips are bonded to each other to form the chip-on-chip structure.
In accordance with an inventive aspect, the semiconductor chip for the chip-on-chip structure is characterized in that a lead frame is fitted on the back face of the primary chip, and the back mark is provided in a predetermined position on the lead frame.
With this arrangement, the fitting of the lead frame is easy, and the formation of the chip-on-chip structure can be achieved by utilizing the back mark on the lead frame in the same manner as the back mark on the primary chip.
In accordance with an inventive aspect, there is provided a chip-on-chip semiconductor device, which comprises a first semiconductor chip disposed with a front face thereof upward, and a second semiconductor chip bonded to the first semiconductor chip with a front face thereof facing downward as opposed to the front face of the first semiconductor chip, wherein a back mark is provided on a back face of the second semiconductor chip so that the first and second semiconductor chips are positioned with respect to each other on the basis of the back mark.
The back mark preferably includes at least two back marks.
In the chip-on-chip semiconductor device, a front mark may be provided on the front face of the first semiconductor chip in a predetermined positional relationship with the back mark, and the first and second semiconductor chips have been positioned with respect to each other by bringing the back mark and the front mark into the predetermined positional relationship.
With this arrangement, the chip-on-chip semiconductor device can be provided in which the first and second semiconductor chips are properly positioned with respect to each other and bonded to each other.
Further, it can be checked whether or not the positioning of the semiconductor chips with respect to each other is proper.
In accordance with an inventive aspect, there is provided a chip-on-chip mounting method, which comprises the steps of: placing a first semiconductor chip with a front face thereof upward; and positioning a second semiconductor chip with respect to the first semiconductor chip on the basis of a back mark provided on a back face of the second semiconductor chip to bond the first and second semiconductor chips to each other in a stacked relation with a front face of the second semiconductor chip kept in a predetermined relation with the front face of the first semiconductor chip.
In accordance with an inventive aspect, there is provided a chip-on-chip mounting method, which comprises the steps of: placing a first semiconductor chip having a back mark provided on a back face thereof with a front face thereof upward; and positioning a second semiconductor chip with respect to the first semiconductor chip on the basis of the back mark provided on the first semiconductor chip to bond the first and second semiconductor chips to each other in a stacked relation with a front face of the second semiconductor chip kept in a predetermined relation with the front face of the first semiconductor chip.
In the aforesaid mounting methods, a front mark to be brought into a predetermined positional relationship with the back mark provided on the second or first semiconductor chip may be provided on the front face of the first or second semiconductor chip not provided with the back mark, and the positioning may be achieved by bringing the back mark and the front mark into the predetermined positional relationship.
This arrangement provides a practical assembling method for a chip-on-chip semiconductor device. In other words, the assembling method for the chip-on-chip semiconductor device can be employed for practical applications on a production line or the like.
In these mounting methods, provision of two or more back marks is advantageous in practical applications.
Further, it can be checked whether or not the positioning of the first and second semiconductor chips with respect to each other is proper in the chip-on-chip structure obtained through any of these methods.
In accordance with the present invention, the semiconductor chips, the semiconductor devices and the mounting methods are provided for realizing the chip-on-chip structure.
In accordance with an inventive aspect, there is provided a semiconductor chip to be employed for assembling a chip-on-chip structure in which semiconductor chips are bonded to each other in a face-to-face stacked relation, the semiconductor chip comprising an informational notation specific thereto provided on a back face thereof to be utilized at least when the chip-on-chip structure is assembled.
In accordance with an inventive aspect, there is provided a chip-on-chip semiconductor device which comprises a plurality of semiconductor chips bonded to one another in a face-to-face stacked relation, wherein at least one of the stacked semiconductor chips has an informational notation specific thereto provided on a back face thereof.
In the chip-on-chip semiconductor device, the plurality of semiconductor chips each have an informational notation specific thereto provided on a back face thereof.
The specific informational notation preferably includes at least one informational notation selected from a model designation of the semiconductor chip, a production lot number of the semiconductor chip and an alignment mark to be utilized for assembling a chip-on-chip structure by employing the semiconductor chip.
The specific informational notation is preferably represented by a bar code and a two-dimensional code.
The semiconductor chip for the chip-on-chip structure in accordance with one aspect of the invention is mounted on another semiconductor chip on the basis of the specific informational notation provided on the back face of the semiconductor chip for assembling the chip-on-chip structure.
More specifically, if an alignment mark for recognition of the orientation of the semiconductor chip, the electrode arrangement on the semiconductor chip or the like is provided as the informational notation, the semiconductor chip can easily be positioned with respect to another semiconductor chip on the basis of the alignment mark so as to be mounted on the another chip with the front face thereof downward.
The specific informational notation may be a human-recognizable notation, or may be a notation optically detectable by an OCR, or a bar-code notation. Alternatively, a plurality of notations may be provided in different forms in combination.
When the chip-on-chip structure is to be assembled, proper semiconductor chips are selected from different types of semiconductor chips by reading the specific informational notations, and positioning information is obtained by reading the informational notations by an assembling robot.
After the assembling of the chip-on-chip structure, whether or not the semiconductor chips have properly been assembled into the chip-on-chip structure can easily be checked on the basis of the informational notations.
With one arrangement of the instant invention, whether or not predetermined semiconductor chips are employed as components of the chip-on-chip semiconductor device can easily be checked by reading the specific informational notations provided on the respective semiconductor chips.
Further, whether or not the assembled state of the device, e.g., the orientation, position and the like of each of the semiconductor chips, is proper can be judged on the basis of the specific informational notations.
The chip-on-chip semiconductor device is molded and then delivered to the market and, when a need arises to check makers and the like of the respective semiconductor chips incorporated in the semiconductor device, the back faces of the semiconductor chips are exposed from a mold package for checking the specific informational notations of the semiconductor chips. Thus, production information on the semiconductor chips can be checked.
In accordance with an inventive aspect, there is provided a semiconductor chip for a chip-on-chip structure in which a plurality of semiconductor chips are bonded to one another in a face-to-face stacked relation, the semiconductor chip having a positioning pin hole extending therethrough from a front face to a back face thereof for recognition of an electrode arrangements an electrode type and the like from the back side thereof.
With one of the arrangements according to the instant invention, the positioning pin hole is formed in the semiconductor chip for the chip-on-chip structure as extending therethrough from the front face to the back face thereof. When the chip-on-chip structure is assembled, the predetermined positioning of the semiconductor chip can be performed on the basis of the positioning pin hole from the back side thereof, so that the semiconductor chip can easily be positioned on a front face of another semiconductor chip with a high level of precision by viewing the semiconductor chip from the back side thereof.
Since the positioning can easily be achieved, the time required for the assembling of the chip-on-chip structure can be reduced advantageously for practical applications.
Where a plurality of positioning pin holes are formed in the semiconductor chip, the orientation of the mounted semiconductor chip can correctly be checked on the basis of the plurality of positioning pin holes.
In accordance with another inventive aspect, there is provided a chip-on-chip semiconductor device, which comprises a first semiconductor chip disposed with a front face thereof upward, and a second semiconductor chip bonded to the first semiconductor chip with a front face thereof facing downward as opposed to the front face of the first semiconductor chip, wherein the second semiconductor chip has a positioning pin hole extending therethrough from the front face to a back face thereof so that the first and second semiconductor chips are positioned with respect to each other on the basis of the positioning pin hole.
With this arrangement, the first and second semiconductor chips bonded to each other in a properly positioned state can be incorporated in the chip-on-chip semiconductor device.
In accordance with another inventive aspect, there is provided a chip-on-chip mounting method, which comprises the steps of: placing a first semiconductor chip with a front face thereof upward; and positioning a second semiconductor chip having a positioning pin hole with respect to the first semiconductor chip on the basis of a positioning pin hole formed in the second semiconductor chip to bond the first and second semiconductor chips to each other in a stacked relation with a front face of the second semiconductor chip kept in a predetermined positional relation with the front face of the first semiconductor chip.
This arrangement provides a practical mounting method for a chip-on-chip semiconductor device. That is, the chip-on-chip mounting method can be employed for practical applications on a production line and the like, and the chip-on-chip structure can be assembled in a shorter time.
Embodiments of the present invention will hereinafter be described with reference to the attached drawings.